This present invention relates to digital CMOS voltage interface circuits, particularly, voltage interfaces which transfer the digital signal between any two voltages, with minimal power dissipation. The interfaces may contain circuitry operating at both involved voltages (power supplies), or they may contain circuitry operating to only one power supply.
CMOS is the principal technology used today to implement digital as well as analog applications. Today, practically all high performance digital circuits are based on CMOS. When scaling a CMOS technology, the supply voltages are decreased to control the magnitude of the electric fields inside the transistors. In addition to controlling the velocity of the electron flow, another beneficial aspect of voltage scaling is a quadratic decrease in dynamic power dissipation with supply voltage as expressed by PD=CLV2DDf. However, a tradeoff occurs, since decreasing the power supply also decreases the circuit speed. As a consequence, different circuit blocks operating at different power supplies are often found in modern processors, such as high speed blocks operating at 5 volts for the critical paths, while the rest of the processor operates at 3.3 volts. Multiple on-chip power supplies are also found in other circuit families such as in mixed signal circuits. Therefore, high performance interfaces are frequently necessary. The signal transfer between low-to-high voltage levels and high-to-low voltage levels has to be performed with minimum delay and power in order to maintain any advantages obtained from using multiple power supplies.
A prior art CMOS interface circuit for converting a low voltage (e.g., 3 V) signal into a high voltage (e.g., 5 V) signal is shown in FIG. 1. If Out1 is low, P5 is on, N5 is off, and Out2 is high. If Out1 is high, both P5 and N5 are on. To make Out2 go low, N5 must have a higher transconductance than P5. Significant static power dissipation is therefore generated during the time Out1 is high. A small P5, however, affects the low-to-high transition of Out2, increasing this transition time. Different interface circuits have been developed to solve those problems and provide an efficient interface, but have not been completely satisfactory.
It is therefore an object of this invention to provide improved interface circuits that are characterized by low power dissipation and minimal delay from input to output.
Another object of this invention is to provide an improved interface circuit that provides at the output, a high driving strength capability with minimal delay and power dissipation.
Another object of this invention is to provide an improved interface circuit that provides the signal voltage exchange while being equivalent in logic function to an inverter, providing a delay equivalent to the delay of an inverter.
Yet another object of this invention is to provide an improved voltage interface circuit with no practical limitations on the magnitude of the voltage levels of the two CMOS families being interfaced, as well as to maintain the same circuit configuration and transistor sizes for both the low-to-high and high-to-low voltage interfaces.
Another object of this invention is to provide an improved interface circuit that operates at one voltage (power supply) with minimal power dissipation.
Briefly described, an interface circuit embodying the invention has an interface block which has two branches which, respectively, receive from an in input block two signals corresponding to an input, which change in polarity in opposite senses, and pass them to an output via a buffer block in which the signals are combined.